module priorityMuxer4 (
    input wire clk,
    input wire rst,
    input wire write_en_1,
    input wire [5:0] priority_1,
    input wire write_en_2,
    input wire [5:0] priority_2,
    input wire write_en_3,
    input wire [5:0] priority_3,
    input wire write_en_4,
    input wire [5:0] priority_4,
    output reg [3:0] priority_arbitration,
    output reg write_en_out,
    output reg [5:0] priority_out
);  
    //优先级仲裁结果
    wire [3:0] arbitration;
    wire [5:0] spriority [0:3];
    assign spriority[0] = write_en_1==1 ? priority_1 : 0;
    assign spriority[1] = write_en_2==1 ? priority_2 : 0;
    assign spriority[2] = write_en_3==1 ? priority_3 : 0;
    assign spriority[3] = write_en_4==1 ? priority_4 : 0;

    always @(posedge clk) begin
        if (rst) begin
            write_en_out <= 1'b0;
            priority_out <= 0;
        end
        else begin
            priority_arbitration <= arbitration;
            if (arbitration == 4'b0001) begin
                write_en_out <= 1'b1;
                priority_out <= priority_1;
            end

            if (arbitration == 4'b0010) begin
                write_en_out <= 1'b1;
                priority_out <= priority_2;
            end

            if (arbitration == 4'b0100) begin
                write_en_out <= 1'b1;
                priority_out <= priority_3;
            end

            if (arbitration == 4'b1000) begin
                write_en_out <= 1'b1;
                priority_out <= priority_4;
            end

            if (arbitration == 4'b0000) begin
                write_en_out <= 0;
            end
        end
    end
    
    priorityArbiter4 arb(.write_en_1(write_en_1), .priority_1(spriority[0]), .write_en_2(write_en_2), .priority_2(spriority[1]), .write_en_3(write_en_3), .priority_3(spriority[2]), .write_en_4(write_en_4), .priority_4(spriority[3]), .priority_arbitration(arbitration));
endmodule